Method for manufacturing thin film integrated circuit, and element substrate

ABSTRACT

Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. In view of the above described object, one feature of the invention is to provide the steps of forming a separation layer over an insulating substrate and forming a thin film integrated circuit having a semiconductor film as an active region over the separation layer, wherein the thin film integrated circuit is not separated. There is less limitation on the shape of a mother substrate in the case of using the insulating substrate when compared with the case of taking a chip out of a circular silicon wafer. Accordingly, reduction in cost of an IC chip can be achieved.

TECHNICAL FIELD

The present invention relates to a method for manufacturing a thin film integrated circuit which can store much information and an element substrate in which the thin film integrated circuit is manufactured.

BACKGROUND ART

In recent years, there has been an increasing need for a card with an IC chip or a tag with an IC chip capable of contactless data communication in all fields that require automatic identification, such as securities and management of goods. In consideration of application, it is required to manufacture such an IC card or an IC tag at a low cost since most IC cards or IC tags are to be thrown away after use. Cost reduction is required particularly for an IC chip formed with a silicon wafer.

As an application of such an IC chip, an IC chip is put on a part of an animal and is used to control infectious diseases and to assure quality for safety management of livestock. Similarly, vegetables are sold with IC chips which store information on the producer, production area, use of pesticides, and the like for safety management of vegetables.

As another application, it is proposed that an IC chip is mounted on securities to prevent abuse thereof and to allow the securities to be reused when they are returned to the regular manager (Reference 1: Japanese Patent Laid-Open No. 2001-260580).

DISCLOSURE OF INVENTION

Reduction in cost of such an IC chip formed with a silicon wafer is close to the limit. However, the diversity of application of an IC chip and the demand for an IC chip are expected to increase, and further cost reduction is required.

Thus, it is an object of the invention to provide a structure and a process which enable production at a much lower cost.

In view of the above object, one feature of the invention is that a thin film integrated circuit (also referred to as an IDF chip or a semiconductor device) is formed over a substrate having an insulating surface (insulating substrate), the insulating substrate is separated, and IDF chips are prevented from being separated from each other.

When an IDF chip is formed over an insulating substrate in this manner, there is less limitation on the shape of a mother substrate, compared with the case of taking a chip out of a circular silicon wafer. Thus, the productivity of an IDF chip can be improved and mass production thereof can be performed. Accordingly, the cost of an IDF chip can be reduced. An IDF chip whose unit price is very low can generate huge profits by reducing unit cost.

In addition, the insulating substrate can be reused by separating the insulating substrate. Therefore, the invention can realize lower cost than a conventional IC chip which is thinned by polishing a silicon wafer.

An extremely thin IDF chip can be manufactured by separating an insulating substrate. After separated from the insulating substrate, the IDF chip may be transferred to another insulating substrate (also referred to as a transfer substrate). At this time, the transfer substrate is preferably a substrate having flexibility (hereinafter also referred to as a flexible substrate). In some cases, transferring an element of an IDF chip (including the one in process of manufacturing) to another substrate as described above is referred to as “transfer”.

A specific feature of the invention is that an insulating substrate is separated by removing a separation layer formed over the insulating substrate. A method for removing the separation layer includes a chemical removal method with the use of an etchant (gas or liquid) and a physical removal method with stress applied. In particular, it is preferable to chemically remove the separation layer with the use of an etchant, since generation of a residue or the like can be suppressed. It is more preferable to remove the separation layer by forming a groove reaching the separation layer and by introducing an etchant into the groove. A gas or liquid including halide can typically be used as the etchant. For example, ClF₃ (chlorine trifluoride), NF₃ (nitrogen trifluoride), BrF₃ (bromine trifluoride), or HF (hydrogen fluoride) can be used as halide.

For example, when an antenna is separately formed and then attached, a substrate to be provided with an antenna (referred to as an antenna substrate) is attached. Thereafter, the separation layer can be removed. In other words, an antenna substrate is provided with an opening and is attached to an insulating substrate that is provided with an IDF chip and a groove; thereafter, a separation layer is chemically removed with an etchant. Accordingly, antennas can be attached to integrated IDF chips without being separated from each other.

As another means to prevent IDF chips from being separated from each other, a part of an insulating film or a conductive film formed between IDF chips is left unremoved while forming a groove (the unremoved region is referred to as a connection region). In this case, the separation layer is removed by an etchant introduced from the selectively formed groove. At this time, the IDF chips are integrated without being separated from each other since the IDF chips are connected to each other by the connection region. Subsequently, an antenna is formed if necessary.

One feature of an element substrate in which an IDF chip is manufactured as described above is to have an insulating substrate provided with a plurality of thin film integrated circuits with a separation layer therebetween, an antenna substrate placed opposite to the insulating substrate, wherein the antenna substrate is provided with an antenna and an opening, and a groove is provided between the thin film integrated circuits to correspond to the opening.

One feature of an element substrate having another structure is to have an insulating substrate provided with a plurality of thin film integrated circuits with a separation layer therebetween, an antenna substrate placed opposite to the insulating substrate, wherein the plurality of thin film integrated circuits are integrated by a connection region, the antenna substrate is provided with an antenna and an opening, a groove is provided between the thin film integrated circuits to correspond to the opening, and an opening is provided in the thin film integrated circuit.

When an IDF chip is formed over an insulating substrate in this manner, there is less limitation on the shape of a mother substrate compared with the case of taking a chip out of a circular silicon wafer. Therefore, the productivity of an IDF chip can be improved and mass production thereof can be performed. Accordingly, the cost of an IDF chip can be reduced. An IDF chip whose unit price is very low can generate huge profits by reducing unit cost.

For example, the number of chips in the case of using a silicon wafer with a diameter of 12 inches is compared with that in the case of using a glass substrate with a size of 7300×9200 mm². The area of the former, the silicon wafer, is about 73000 mm² whereas the area of the latter, the glass substrate, is about 672000 mm². The glass substrate is about 9.2 times as large as the silicon substrate. The glass substrate with an area of about 672000 mm² can be provided with, leaving out of consideration the cutting margin, about 672000 IDF chips of 1 mm square, which is about 9.2 times as many as the silicon substrate. Since mass production of the IDF chip using the glass substrate with a size of 7300×9200 mm² can be achieved with fewer steps than the case of using the silicon substrate with a diameter of 12 inches, the amount of capital investment can be reduced to one-third.

When IDF chips are manufactured without being separated from each other as described above, there is no concern that an exhaust system of an apparatus is clogged with IDF chips during processing. The complexity of handling very small IDF chips can be reduced. A thin IDF chip formed over a large substrate might warp due to stress. However, the warpage can be prevented by manufacturing IDF chips to be integrated. In particular, warpage prevention effect can be enhanced by providing a connection region between the IDF chips.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B show a step of manufacturing a thin film integrated circuit.

FIGS. 2A to 2C show a step of manufacturing a thin film integrated circuit.

FIGS. 3A to 3C show a step of manufacturing a thin film integrated circuit.

FIGS. 4A to 4C show a step of manufacturing a thin film integrated circuit.

FIGS. 5A to 5C show a step of manufacturing a thin film integrated circuit.

FIGS. 6A to 6C show a step of manufacturing a thin film integrated circuit.

FIGS. 7A and 7B show a step of manufacturing an antenna.

FIGS. 8A to 8C show a step of manufacturing a thin film integrated circuit.

FIGS. 9A to 9C show a step of manufacturing a thin film integrated circuit.

FIGS. 10A to 10C show a step of manufacturing a thin film integrated circuit.

FIGS. 11A to 11C show a step of manufacturing a thin film integrated circuit.

FIGS. 12A to 12C show a step of manufacturing a thin film integrated circuit.

FIGS. 13A to 13C show a step of manufacturing a thin film integrated circuit.

FIGS. 14A to 14E show a step of manufacturing a thin film integrated circuit.

FIGS. 15A and 15B show an article mounted with a thin film integrated circuit.

FIGS. 16A to 16C show an article mounted with a thin film integrated circuit.

FIGS. 17A and 17B show an article mounted with a thin film integrated circuit.

FIG. 18A shows an application of an article mounted with a thin film integrated circuit and FIG. 18B shows a circuit configuration of an IDF chip and a reader/writer.

FIGS. 19A and 19B show a bent article mounted with a thin film integrated circuit.

FIGS. 20A and 20B show a step of manufacturing a thin film integrated circuit.

FIGS. 21A and 21B show a step of manufacturing a thin film integrated circuit.

FIGS. 22A to 22C show a mode of a thin film integrated circuit.

FIGS. 23A and 23B show a step of manufacturing a thin film integrated circuit.

FIG. 24 shows a manufacturing apparatus of a thin film integrated circuit.

FIGS. 25A to 25D show a step of manufacturing a thin film integrated circuit.

FIGS. 26A and 26B show a step of manufacturing a thin film integrated circuit.

FIG. 27 shows an article mounted with a thin film integrated circuit.

FIG. 28 shows an article mounted with a thin film integrated circuit.

FIG. 29 shows an article mounted with a thin film integrated circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

Preferred embodiments of the present invention are hereinafter described with reference to attached drawings. The present invention is not limited to the following description. As is easily known to a person skilled in the art, the mode and the detail of the invention can be variously changed without departing from the purpose and the scope of the present invention. Thus, the present invention is not interpreted while limiting to the following description of the embodiment mode. Note that the same reference numeral is given to the same portion or a portion having a similar function among diagrams for showing the embodiment mode, and repetitive description is omitted.

Embodiment Mode 1

A mode of removing a separation layer after attaching an antenna substrate is described in this embodiment mode.

As shown in FIG. 1A, a separation layer 102 and a thin film transistor (also referred to as a TFT) layer 103 having a semiconductor film as an active region are sequentially formed over an insulating substrate 100, thereby forming a plurality of IDF chips 104. Although a detailed structure of the TFT layer is to be described below, the semiconductor film is formed to be 0.2 μm or less, typically, 40 nm to 170 nm, and preferably, 50 nm to 150 nm in thickness.

Because of having an extremely thin semiconductor film as an active region, the IDF chip can be made thinner than a chip formed with a silicon wafer. A specific thickness of the IDF chip is 0.3 μm to 3 μm, typically, approximately 2 μm.

Then, a groove 105 is formed on the TFT layer at the boundary between the IDF chips. The groove can be formed by dicing, scribing, etching with the use of a mask, or the like. The groove is formed to have such a depth as to expose the separation layer. Note that the groove need not necessarily be formed at every boundary between the IDF chips, but it may be formed at intervals of boundaries between the IDF chips.

As shown in FIG. 21A, an opening 108 may be formed in the TFT layer 103. The opening needs to be formed in the TFT layer 103 except in a region where the semiconductor film is formed. When such an opening is utilized in combination with the groove, the size of the groove can be reduced and the time needed to remove the separation layer can be shortened.

A substrate made of glass such as barium borosilicate glass or alumino borosilicate glass; a quartz substrate; or the like can be used as the insulating substrate. In addition, a substrate made of a synthetic resin such as plastic typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyether sulfone (PES) or acrylic can be used as another substrate having an insulating surface. A metal such as stainless steel, a semiconductor substrate, or the like provided on the surface thereof with an insulating film of silicon oxide, silicon nitride, or the like can also be used. In the case of using such an insulating substrate, there is less limitation on the shape of a mother substrate, compared with the case of taking a chip out of a circular silicon wafer. Therefore, reduction in cost of an IDF chip can be achieved.

The separation layer is only necessary to be a film containing silicon, which may be in any condition of an amorphous semiconductor, a semi-amorphous semiconductor (also referred to as a SAS) in which an amorphous state and a crystalline state are mixed, and a crystalline semiconductor. Note that the SAS includes a microcrystalline semiconductor in which a crystal grain of 0.5 nm to 20 nm can be observed within an amorphous semiconductor. The separation layer can be formed by a sputtering method, a plasma CVD method, or the like. The thickness of the separation layer is preferably in the range of 30 nm to 1 μm, and can even be 30 nm or less, provided that the thickness does not fall below a minimum thickness determined for the film formation apparatus.

The separation layer may be added with an element such as phosphorus or boron. The element may be activated by heating or the like. A reaction rate, that is, an etching rate of the separation layer can be increased by adding the element.

A base film is formed over the separation layer so that the TFT layer is not etched. The base film has a single layer structure of an insulating film containing oxygen or nitrogen such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiOxNy) (x>y) film, or a silicon nitride oxide (SiNxOy) (x>y) (x, y=1, 2 . . . ) film or has a laminated structure thereof.

An antenna substrate 111 is provided with a plurality of antennas 112 having a predetermined shape and is suitably provided with an opening 113. The opening has a circular shape (corresponding to a so-called hole), a rectangular shape (corresponding to a so-called slit), or the like. In addition, the opening is preferably formed to overlap the groove 105.

The insulating substrate 100 is attached to the antenna substrate 111 with an adhesive or the like. An anisotropic conductor including a dispersed conductor, an ultrasonic adhesive, or an ultraviolet curing resin can be used as the adhesive.

As shown in FIG. 1B, an etchant 115 is introduced into the opening and the groove with the antenna substrate attached to the insulating substrate to remove the separation layer. A gas or liquid including halide typified by ClF₃ is employed as the etchant.

The insulating substrate is separated after the separation layer is removed. Thereafter, each IDF chip is cut by a dicing, scribing, or laser cutting method. For example, each IDF chip can be cut by using a laser which is absorbed by a glass substrate, such as a CO₂ laser. The periphery of the IDF chip such as a side face may be covered with an organic resin such as an epoxy resin. Accordingly, the IDF chip is protected from outside and becomes easily portable. The thus formed IDF chip can be 5 mm squared (25 mm²) or less, preferably, 0.3 mm squared (0.09 mm²) to 4 mm squared (16 mm²).

The IDF chip of the invention can be completed without an insulating surface and be mounted on an article. Therefore, the IDF chip can be thinned and reduced in weight, and the article mounted therewith can also be thinned and reduced in weight as a whole.

The IDF chip that is separately transferred to a transfer substrate may be mounted. The transfer substrate is preferably a flexible substrate. A substrate made of a synthetic resin such as plastic typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyeter sulfone (PES) or acrylic can be used as the flexible substrate.

A thermosetting resin, an ultraviolet curing resin, an epoxy resin, a resin additive, two-sided tape, or the like can be used as an adhesive for attaching the flexible substrate.

As a result of transferring the IDF chip to the flexible substrate, the breaking strength of the IDF chip can be increased. The IDF chip transferred to the flexible substrate can be made more lightweight, thinner, and more flexible than the IDF chip formed over the insulating substrate.

The separated insulating substrate can be reused. Accordingly, reduction in cost of the IDF chip can be achieved. In the case of reuse, dicing, scribing, or the like in forming the groove is preferably controlled, not to damage the insulating substrate. However, even when the insulating substrate is damaged, planarizing treatment can be performed by forming an organic resin or an inorganic film by an application method or a droplet discharge method. Note that a droplet discharge method is a method for selectively discharging (spraying) a droplet (also referred to as a dot) of a composition mixed with a material of a conductive film, an insulating film, or the like, which is also referred to as an ink-jet method depending on its mode.

When the IDF chip is formed over the substrate with an insulating surface, as described above, there is less limitation on the shape of a mother substrate, when compared with the case of taking a chip out of a circular silicon wafer. Therefore, the productivity of an IDF chip can be improved and mass production thereof can be performed. Since the insulating substrate can be reused, the cost of an IDF chip can be reduced. Accordingly, reduction in cost of the IDF chip can be achieved.

The IDF chip has a semiconductor film of 0.2 μm or less as an active region and is very thin unlike a chip formed with a silicon wafer. In order to increase the strength of such a thin IDF chip, the method for transferring to a flexible substrate can be employed. Such a thin, lightweight, or highly flexible IDF chip is harder to damage than a chip formed with a silicon wafer.

The IDF chip is in no danger of wave absorption and has good reception of signals compared to a chip formed with a silicon wafer. Since the IDF chip does not have a silicon wafer, it can be light-transmitting.

Note that the case of attaching the IDF chip to the antenna is described in this embodiment mode; however, the antenna may be directly formed over the IDF chip. The separation of the IDF chips can be prevented by providing an opening on not an antenna substrate but an insulating substrate where an antenna is not located. Thus, the effect of the invention can be obtained.

Specifically, the IDF chip includes a contactless IDF chip mounted with an antenna (also referred to as an RFID tag or an RFID chip, or an RFID memory or an RFID processor depending on the application), a contact IDF chip provided with a terminal connected to an external power source without an antenna mounted, and a hybrid IDF chip which is a combination of a contactless type and a contact type.

The contactless IDF chip is described in this embodiment mode, but it may also be either a contact IDF chip or a hybrid IDF chip. Even in the case of a contact IDF chip without an antenna, the separation of the IDF chips can be prevented by providing an opening on not an antenna substrate but an insulating substrate where an antenna is not located. Thus, the effect of the invention can be obtained.

Embodiment Mode 2

A mode of selectively forming a groove and partially leaving an insulating film, a conductive film, or the like provided between IDF chips is described in this embodiment mode.

As shown in FIG. 8A, a separation layer 102 and a TFT layer 103 are sequentially formed over an insulating substrate 100, thereby forming a plurality of IDF chips 104 similarly as in Embodiment Mode 1. Note that details of the TFT layer are to be described below.

Since a groove 105 formed at the boundary between the IDF chips is selectively formed, an insulating film, a conductive film, or the like is left between the IDF chips. Such an insulating film, a conductive film, or the like between the IDF chips is referred to as a connection region 106. Note that the connection region may have a function of connecting the IDF chips to be integrated and may have either a single layer structure or a laminated structure.

As shown in FIG. 21B, an opening 108 may be formed in the TFT layer 103. The opening needs to be formed in the TFT layer 103 except in a region where the semiconductor film is formed. When such an opening is utilized in combination with the groove, the size of the groove can be reduced or the time needed to remove the separation layer can be shortened.

As shown in FIG. 8B, an etchant 115 is introduced into the groove 105 to remove the separation layer. A gas or liquid including halide typified by ClF₃ can be employed as the etchant as in Embodiment Mode 1.

At this time, the reaction time and introduction quantity are adjusted so that the separation layer formed below the connection region 106 is also removed. The separation layer below the connection region recedes to be removed. Consequently, the insulating substrate is separated; however, the IDF chips are not separated from each other since they are integrated by the connection region.

The separated insulating substrate can be reused as in Embodiment Mode 1.

Thereafter, an antenna is formed if necessary as shown in FIG. 8C. An antenna 112 formed over an antenna substrate 111 is attached in this embodiment mode. At this time, the antenna substrate may not contain an opening.

Thereafter, the IDF chips are cut by a dicing, scribing, or laser cutting method. For example, the IDF chips can be cut by using a laser which is absorbed by a glass substrate, such as a CO₂ laser. The periphery of the IDF chip such as a side face may be covered with an organic resin such as an epoxy resin as in Embodiment Mode 1.

In this embodiment mode, the IDF chip can be completed without being transferred to a transfer substrate. Therefore, the IDF chip can be thinned and reduced in weight, and the article mounted therewith can also be thinned and reduced in weight as a whole. The IDF chip may be transferred to a transfer substrate as in Embodiment Mode 1. Accordingly, the breaking strength of the IDF chip can be increased.

Embodiment Mode 3

A mode of attaching the antenna substrate which is provided with an opening, as described in Embodiment Mode 1, to the insulating substrate which is provided with a connection region between IDF chips, as described in Embodiment Mode 2, is described in this embodiment mode.

As shown in FIG. 20A, a separation layer 102 and a TFT layer 103 are sequentially formed over an insulating substrate 100, and a groove 105 is selectively formed to have a connection region 106 between IDF chips 104, as in Embodiment Mode 2.

Thereafter, an antenna substrate 111 provided with an antenna 112 and an opening 113 is attached thereto as in Embodiment Mode 1. At this time, the antenna substrate is preferably attached to position the opening 113 to the groove 105.

As shown in FIG. 20B, an etchant 115 is introduced into the opening and the groove. Then, the separation layer is removed and the insulating substrate 100 can be separated. At this time, the IDF chips are not separated from each other since they are integrated by the connection region and the antenna substrate.

The case of introducing an etchant after attaching the antenna substrate is described in this embodiment mode; however, an etchant may be introduced before attaching the antenna substrate. Even in that case, the insulating substrate can be separated without separating the IDF chips from each other since the IDF chips are integrated by the connection region.

Thereafter, the IDF chips are cut by a dicing, scribing, or laser cutting method. For example, the IDF chips can be cut by using a laser which is absorbed by a glass substrate, such as a CO₂ laser.

Thereafter, the periphery of the IDF chip such as a side face may be covered with an organic resin such as an epoxy resin as in Embodiment Mode 1.

In this embodiment mode, the IDF chip can be completed without being transferred to a transfer substrate. However, the IDF chip may be transferred to a transfer substrate as in Embodiment Mode 1. Accordingly, the breaking strength of the IDF chip can be increased.

Embodiment 1

A method of the mode described in Embodiment Mode 1 is described in more detail in this embodiment.

FIG. 2A is a top view in the case of forming 12 IDF chips over an insulating substrate 100, FIG. 2B is a cross-sectional view of line a-b from FIG. 2A, and FIG. 2C is a cross-sectional view of line c-d from FIG. 2A.

As shown in FIG. 2B, a TFT layer formed over the insulating substrate 100 with a separation layer 102 therebetween includes thin film transistors 128 n and 128 p, each having an insulating film, a semiconductor film 124 patterned into a desired shape, an insulating film which functions as a gate insulating film (hereinafter referred to as a gate insulating film) 125, and a conductive film which functions as a gate electrode (hereinafter referred to as a gate electrode) 126. The semiconductor film includes a channel formation region and an impurity region (including a source region, a drain region, a GOLD region, and an LDD region) and can be divided into an n-channel thin film transistor 128 n and a p-channel thin film transistor 128 p depending on the conductivity of an added impurity element. The semiconductor film also includes a wiring 130 formed to connect to each impurity region.

In this embodiment, a SAS having thicknesses of 30 nm to 1 μm, preferably, 30 nm to 50 nm is used as the separation layer; however, another material described above may be used.

The insulating film may have a laminated structure and has a first insulating film 121, a second insulating film 122, and a third insulating film 123 in this embodiment. For example, a silicon oxide film is used as the first insulating film; a silicon oxynitride film, as the second insulating film; and a silicon oxide film, as the third insulating film. Considering impurity diffusion from the substrate or the like, a silicon oxynitride film is preferably used. However, there is concern that the silicon oxynitride film has poor adhesion with the separation layer and the semiconductor film. Therefore, it is preferable to provide a silicon oxide film which has good adhesion with the separation layer, the semiconductor film, and the silicon oxynitride film.

The semiconductor film 124 may be in any condition of an amorphous semiconductor, a SAS in which an amorphous state and a crystalline state are mixed, a microcrystalline semiconductor in which a crystal grain of 0.5 nm to 20 nm can be observed within an amorphous semiconductor, and a crystalline semiconductor.

In the case of using a substrate which can withstand a film formation processing temperature, for example, a quartz substrate, a crystalline semiconductor film may be formed over the substrate by a CVD method or the like.

In this embodiment, an amorphous semiconductor film is formed and heat-treated to form a crystallized crystalline semiconductor film. A heating furnace, laser irradiation, irradiation with light emitted from a lamp in place of laser light (hereinafter referred to as lamp annealing), or a combination thereof can be employed as the heat treatment.

A continuous wave laser (CW laser) or a pulsed wave laser (pulsed laser) can be used in the case of employing laser irradiation; one of or a plurality of an Ar laser, a Kr laser, an excimer laser, a YAG laser, a Y₂O₃ laser, a YVO₄ laser, a YLF laser, a YAlO₃ laser, a glass laser, a ruby laser, an alexandrite laser, a Ti:sapphire laser, a copper vapor laser, and a gold vapor laser may be used. A crystal having a large grain size can be obtained by irradiation with a fundamental wave of the above laser and a second harmonic to a fourth harmonic of the fundamental wave. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd:YVO₄ laser (fundamental wave of 1064 nm) can be used. Energy density of the laser at the time needs to be in the range of approximately 0.01 MW/cm² to 100 MW/cm² (preferably, 0.1 MW/cm² to 10 MW/cm²). Then, laser irradiation is performed at scanning speed of approximately 10 cm/sec to 2000 cm/sec.

For example, crystallization is performed with the use of an optical system as shown in FIG. 23A and a CW laser. First, a CW laser beam emitted from a laser oscillator 290 is elongated by an optical system 291 and is processed into a linear shape. Specifically, a laser beam can be processed into a linear shape when the laser beam passes a cylindrical lens or a convex lens included in the optical system 291. The laser beam is preferably processed to have a spot long axis length of 200 μm to 350 μm.

Thereafter, the laser beam processed into a linear shape enters the semiconductor film 124 through a galvanometer mirror 293 and an fθ lens 294. At this time, the linear laser is adjusted to form a laser spot 282 having a predetermined size on the semiconductor film. In addition, the fθ lens 294 makes the shape of the laser spot 282 constant on the surface of an irradiated object, regardless of the angle of the galvanometer mirror.

At this time, a device (control device) 296 for controlling the vibration of the galvanometer mirror vibrates the galvanometer mirror, in other words, changes the angle of the mirror. The laser spot 282 is moved in one direction (for example, in an X-axis direction in the figure). For example, when the galvanometer mirror vibrates in half cycle, the laser spot is moved in an X-axis' direction on the semiconductor film by a certain width (outward).

Then, the semiconductor film is moved on a Y-axis direction by an XY stage 295. The laser spot is moved on an X-axis direction on the semiconductor film by the galvanometer mirror in the same manner (homeward). With such back-and-forth movement of the laser beam, the laser spot is moved along a pathway 283 to perform the laser annealing on the entire semiconductor film.

As shown in FIG. 23B, the laser annealing is performed on the thin film transistor so that a carrier flow direction 281 and a moving direction of the laser beam to a long axis (scanning direction) are in the same direction. For example, in the case of a semiconductor film 230 having such a shape as shown in FIG. 23B, a source region 230(s), a channel formation region 230(c), and a drain region 230(d) formed in the semiconductor film are arranged to be parallel to the moving direction of the laser beam to a long axis (scanning direction). Consequently, grain boundaries through which carriers pass can be reduced or eliminated; therefore, mobility of the thin film transistor can be improved.

In addition, the laser may have an incident angle θ (0<θ<90°) to the semiconductor film. Consequently, laser interference can be prevented.

The semiconductor film may be irradiated with continuous wave laser light of a fundamental wave and continuous wave laser light of a harmonic, or may be irradiated with continuous wave laser light of a fundamental wave and pulsed wave laser light of a harmonic. Energy can be supplemented by irradiating with plural kinds of laser light.

In the case of the pulsed wave laser, pulsed laser may be oscillated with such a repetition rate that the laser of the next pulse is emitted after melting the semiconductor film and before solidifying the semiconductor film. This makes it possible to obtain crystal grains that are sequentially grown in the scanning direction. In other words, it is possible to use a pulsed beam with a low repetition rate limit that is set shorter than the time required for the melted semiconductor film by the preceding beam to solidify.

Actually used is a pulsed beam with repetition rate of 10 MHz or more which are much higher repetition rate than that of several tens to several hundreds Hz of a normally used pulsed beam.

The laser light irradiation may be performed in an inert gas atmosphere such as a noble gas or nitrogen. This can suppress roughness of a semiconductor surface due to the laser light irradiation and prevent variations in the threshold caused by variations in interface state density.

A microcrystalline semiconductor film may be formed by using SiH₄ and F₂, or SiH₄ and H₂ and be then irradiated with the laser as described above for crystallization.

In the case of using a heating furnace as another heat treatment, an amorphous semiconductor film is heated at temperatures of 500° C. to 550° C. for 2 to 20 hours. At this time, the temperature may be set in multiple stages in the range of 500° C. to 550° C. so as to gradually reach a higher temperature. Since hydrogen and the like of the amorphous semiconductor film are released at the first low temperature heating step, so-called dehydrogenation can be performed to reduce film roughness during crystallization. When a metal element which accelerates crystallization, for example, Ni, is further formed over the amorphous semiconductor film, the heat temperature can be lowered, which is preferable. Even in the case of using such a metal element, heat treatment can be performed at high temperatures of 600° C. to 950° C.

However, in the case of forming a metal element, there is concern that the metal element may adversely affect electric characteristics of a semiconductor element. Thus, a gettering step is required to reduce or remove the metal element. For example, the step may be performed to capture the metal element by using the amorphous semiconductor film as a gettering sink.

Alternatively, a crystalline semiconductor film may be directly formed on a formation surface. In this case, the crystalline semiconductor film can be directly formed on a formation surface by utilizing heat or plasma with the use of a fluorine-based gas such as GeF₄ or F₂ and a silane-based gas such as SiH₄ or Si₂H₆. In the case of directly forming the crystalline semiconductor film as described above and requiring high temperature treatment, a quartz substrate that is highly heat resistant may preferably be employed.

The heat treatment of the semiconductor film is considered to affect the separation layer. For example, when the heat treatment is performed by a heating furnace or laser irradiation with a wavelength of 532 nm, energy reaches the separation layer in some cases. Accordingly, the separation layer may also be crystallized at the same time. A reaction rate can be improved depending on a state of crystallization of the separation layer.

On the other hand, in order to effectively crystallize the semiconductor film, the base film can be formed to have a structure that prevents the energy of a laser from reaching the separation layer. For example, materials, film thickness, and laminate order of the base film can be selected.

A semiconductor film formed by any of the above described means contains more hydrogen than a chip formed with a silicon wafer. Specifically, the semiconductor film can be formed to contain hydrogen of 1×10^(·)/cm³ to 1×10²²/cm³, preferably, 1×10¹⁹/cm³ to 5×10²⁰/cm³. The hydrogen can provide a so-called dangling-bond termination effect, which reduces dangling bonds in the semiconductor film. Further, the hydrogen can increase flexibility of the IDF chip.

Further, damage or separation due to bending stress of the thin film transistor can be prevented by making a ratio of an area of the patterned semiconductor film in the IDF chip 1% to 30%.

The thin film transistor having a semiconductor film has a subthreshold coefficient (S-value) of 0.35 V/sec or less, preferably, 0.25 V/sec to 0.09 V/sec. In addition, the thin film transistor has mobility of 10 cm²V/sec or more.

When a 19-stage ring oscillator is formed by using such TFTs, a repetition rate thereof is 1 MH or more, preferably, 100 MHz or more at a power supply voltage of 3 V to 5 V. The delay time per stage of an inverter is 26 ns, preferably, 0.26 ns or less at a power supply voltage of 3 V to 5 V.

According to the above described structure, a function as a TFT can be obtained, but a first interlayer insulating film 127 and a second interlayer insulating film 129 are preferably formed. Damage, defects, or the like of the semiconductor film can be repaired with hydrogen from the first interlayer insulating film. In other words, a termination effect of dangling bonds due to hydrogen can be obtained. An insulating film containing oxygen or nitrogen such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiOxNy) (x>y) film, or a silicon nitride oxide (SiNxOy) (x>y) (x, y=1, 2 . . . ) film can be used as the first interlayer insulating film.

Planarity can be improved by the second interlayer insulating film. An organic material or an inorganic material can be used for the second interlayer insulating film. Polyimide, acrylic, polyamide, polyimide amide, a resist, benzocyclobutene, siloxane, or polysilazane can be used as an organic material. Siloxane is formed by using as a starting material a polymer material in which a skeletal structure is configured by a bond of silicon and oxygen and which contains at least hydrogen as a substituent or which contains at least one of fluorine, an alkyl group, and aromatic hydrocarbon as a substituent. Polysilazane is formed by using as a starting material a liquid material including a polymer material having a bond of silicon (Si) and nitrogen (N). An insulating film containing oxygen or nitrogen such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiOxNy) (x>y) film, or a silicon nitride oxide (SiNxOy) (x>y) (x, y=1, 2 . . . ) film can be used as an inorganic material. In addition, a laminated structure of the insulating films described above may be used for the second interlayer insulating film. When the second interlayer insulating film is formed by using an organic material, planarity is improved; however moisture and oxygen are absorbed by the organic material. An insulating film having an inorganic material is preferably formed over the organic material to prevent that. When an insulating film containing nitrogen is used for the inorganic material, entry of alkali ions such as Na can be prevented.

More preferably, a fourth insulating film 131 is provided to cover the wiring 130. Since an article mounted with the IDF chip is often touched by bare hands, there is concern of diffusion of alkali ions such as Na. Therefore, the fourth insulating film is preferably formed on the top surface of the IDF chip. An insulating film containing oxygen or nitrogen such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiOxNy) (x>y) film, or a silicon nitride oxide (SiNxOy) (x>y) (x, y=1, 2 . . . ) film can be used as the fourth insulating film. Typically, a silicon nitride oxide (SiNxOy) film is preferably used.

Thereafter, a groove 105 is formed between the IDF chips 104. The groove can be formed by dicing, scribing, etching with the use of a mask, or the like. A blade dicing method with a dicing apparatus (dicer) is commonly employed for dicing. The blade is a grinding stone into which a diamond abrasive is embedded, and has widths of approximately 30 μm to 50 μm. The TFT layer is separated by rapidly spinning the blade. A diamond scribing method, a laser scribing method, or the like is used for scribing. In the case of etching, the TFT layer can be separated by dry etching, wet etching, or the like after forming a mask pattern by a light exposure step and a development step. In dry etching, an atmospheric plasma method may be used. Thus, by employing the above described method, a groove can be formed between the IDF chips.

Note that the groove need not necessarily be formed at every boundary between the IDF chips, but it may be formed at intervals of boundaries between the IDF chips.

Subsequently, an antenna substrate is attached as shown in FIGS. 3A to 3C. FIG. 3A is a top view with an antenna substrate 111 attached, FIG. 3B is a cross-sectional view of line a-b from FIG. 3A, and FIG. 3C is a cross-sectional view of line c-d from FIG. 3A.

An anisotropic conductor 141 including dispersed conductors 140 can be used as an attaching means. The anisotropic conductor can electrically join a connection terminal of the IDF chip to a connection terminal of the antenna since the conductors are bonded to each other by pressure due to the thickness of each connection terminal. A region other than the connection terminals remains nonconductive since sufficient distance is kept between the conductors. Instead of an anisotropic conductor, the antenna substrate may be attached with the use of an ultrasonic adhesive, an ultraviolet curing resin, two-sided tape, or the like.

The antenna substrate 111 is provided with an antenna 112 and an opening 113. The position of the antenna corresponds to the IDF chip. As shown in FIG. 3B, the position of the opening 113 corresponds to the groove 105. Detailed manufacturing steps of the antenna and the opening are described below.

In this embodiment, the openings are formed at every boundary between the antennas; however, they may be formed at intervals of boundaries. Further, the case of the opening having a circular shape is also described in this embodiment; however, the invention is not limited thereto. For example, the opening may be formed to have a slit shape. As described above, the shape and the position of the groove 105 and the opening 113 can be appropriately set.

Subsequently, the separation layer is removed by introducing a gas or liquid containing halide typified by ClF₃ as an etchant as shown in FIGS. 4A to 4C. Here, the separation layer is removed by using a low pressure CVD apparatus, shown in FIG. 24, under the following conditions: gas, ClF₃ (chlorine trifluoride); temperature, 350° C.; flow rate, 300 sccm, pressure, 6 Torr; and time, 3 hours. For example, HF can be used as the etchant and a silicon dioxide (SiO₂) can be used as the separation layer.

In addition, the low pressure CVD apparatus shown in FIG. 24 has a bell jar 89 which enables treatment of a plurality of insulating substrates 100. ClF₃ 115 is introduced through a gas introduction pipe, and unnecessary gas is expelled through an exhaust pipe 92. At this time, there is no possibility that the IDF chips are drawn into the exhaust pipe since the IDF chips are integrated by the antenna substrate. Further, a heating means, for example, a heater 91 may be provided on the side face of the apparatus.

FIG. 4A is a top view showing a state of introducing a gas or liquid containing halide typified by ClF₃ to remove a separation layer, FIG. 4B is a cross-sectional view of line a-b from FIG. 4A, and FIG. 4C is a cross-sectional view of line c-d from FIG. 4A.

FIG. 4B shows the state of introducing a gas or liquid containing halide typified by ClF₃ into an opening 113 and a groove 105. When a processing temperature, by a heating means, is in the range of 100° C. to 300° C., the reaction rate can be increased. Consequently, consumption of ClF₃ gas can be reduced and processing time can be shortened.

The separation layer of a SAS gradually recedes by introducing an etchant in this manner. Then, the insulating substrate can be removed as indicated by the arrow.

An etchant, gas flow rate, temperature, and the like are set so that each layer of the TFT is not etched. Since ClF₃ used in this embodiment has a characteristic of selectively etching silicon, it selectively removes the separation layer of a SAS. Therefore, a layer mainly containing silicon typified by a SAS is used as the separation layer, and an insulating film containing oxygen or nitrogen is used as the base film. Since difference in the reaction rate between the separation layer and the base film is large, meaning that the selectivity is high, the separation layer can be easily removed, with the IDF chip protected. In this embodiment, the TFT layer is not etched by ClF₃ due to the base film and a protective film which are provided above and below the TFT layer and edge portions of the interlayer insulating film, the gate insulating film, the wiring, and the like which are exposed on the side face.

Note that ClF₃ can be generated through a process of Cl₂(g)+3F₂(g)→2ClF₃(g) by the reaction of chlorine with fluorine at temperatures of 200° C. or more. ClF₃ (boiling point: 11.75° C.) can liquefy depending on the temperature of the reaction field. In such a case, wet etching can also be employed using ClF₃ as the liquid containing halide.

A gas of ClF₃ or the like mixed with nitrogen may be used as another gas containing halide (typified by ClF₃).

The etchant is not limited to ClF₃ or halide as long as it etches the separation layer and it does not etch the base film. For example, a plasma gas containing fluorine such as CF₄, SF₆, NF₃, or F₂ can be used. A strong alkaline solution such as tetraethylammonium hydroxide (TMAH) may be used as another etchant.

In the case of chemically removing the separation layer with a gas containing halide such as ClF₃, the combination of the separation layer and the base film is not limited to the above-described material as long as the material that is selectively etched is used for the separation layer and a material that is not etched is used for the base film.

Even when the insulating substrate is removed as described above, the IDF chips are integrated by the antenna substrate. Thereafter, the IDF chips are cut by a dicing, scribing, or laser cutting method, thereby completing the IDF chip. Then, the IDF chip may be mounted on an article. A thermosetting resin, an ultraviolet curing resin, an epoxy resin, a resin additive, two-sided tape, or the like can be used as an adhesive for mounting.

Although the IDF chip can be completed according to the above-described step, a flexible substrate may be attached as shown in FIGS. 5A to 5C. FIG. 5A is a top view showing a state of attaching a flexible substrate 150 with an adhesive 151, FIG. 5B is a cross-sectional view of line a-b from FIG. 5A, and FIG. 5C is a cross-sectional view of line c-d from FIG. 5A.

A substrate made of a synthetic resin such as plastic as described above or acrylic can be used as the flexible substrate. In this embodiment, a substrate made of plastic is used.

A thermosetting resin, an ultraviolet curing resin, an epoxy resin adhesive, a resin additive, two-sided tape, or the like can be used as the adhesive.

The breaking strength of the IDF chip can be increased by transferring the IDF chip to the flexible substrate.

The IDF chips are cut by a dicing, scribing, or laser cutting method as shown in FIGS. 6A to 6C, thereby completing the IDF chip formed over the flexible substrate. FIG. 6A is a top view showing the state of the cut IDF chip, FIG. 6B is a cross-sectional view of line a-b from FIG. 6A, and FIG. 6C is a cross-sectional view of line c-d from FIG. 6A.

The thus formed IDF chip may be mounted on an article. A thermosetting resin, an ultraviolet curing resin, an epoxy resin, a resin additive, two-sided tape, or the like can be used as an adhesive for mounting.

The IDF chips which are integrated until just before being completed in this manner can reduce the complexity of handling separated IDF chips. In addition, they may be integrated until just before being mounted on an article. For example, the IDF chips are cut only in one direction in line and placed on an IDF chip mounting apparatus, and then cut in the other direction at the time of mounting on an article. This makes it possible to reduce the complexity of handling separated IDF chips and to easily mount the IDF chips.

Although not shown, the IDF chip may be covered with a resin or an insulating film containing nitrogen for protection, and in particular, the side face of the IDF chip is preferably covered therewith. Protecting the IDF chip improves portability of the IDF chip. The resin or the insulating film containing nitrogen can be made of the same material of as the article to be mounted with the IDF chip.

In this embodiment, the IDF chip is mounted with the use of an anisotropic conductor in a “face-down” manner, where the connection terminal of the IDF chip faces the antenna, as described; however, the IDF chip may also be mounted in a “face-up” manner, where the connection terminal faces in the opposite direction to the antenna. At this time, a wire bonding method can be used as a means for connection.

As described hereinabove, a thin film transistor is formed over the insulating substrate 100, and the insulating substrate 100 is then separated. Preferably, the thin film transistor is further transferred to a flexible substrate. However, the timing of or the number of separations performed is not limited to this embodiment. In addition, the thin film transistor may be mounted on an article (mount article) without transferring the thin film transistor to the flexible substrate. The mounting of the IDF chip in a “face-up” or “face-down” manner is determined in accordance with the number of transfers.

Subsequently, the step of manufacturing an antenna is described with reference to FIGS. 7A and 7B. FIGS. 7A and 7B show a rectangularly winding antenna over an antenna substrate; however, the shape of the antenna is not limited thereto. For example, the antenna may be circular or linear.

A substrate made of glass such as barium borosilicate glass or alumino borosilicate glass; a quartz substrate; a substrate made of a synthetic resin such as plastic typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyeter sulfone (PES) or acrylic can be used as the antenna substrate. Since the antenna substrate is preferably thin, a film substrate is preferred.

As shown in FIG. 7A, an antenna 112 is formed over an antenna substrate 111 by a droplet discharge method with the use of a nozzle 160. The antenna can be formed by any one of the following methods: a sputtering method, a printing method, a plating method, a photolithography method, an evaporation method with the use of a metal mask, and a combination thereof, in lieu of a droplet discharge method. A first antenna is formed by a sputtering method, a droplet discharge method, a printing method, a photolithography method, or an evaporation method, and a second antenna is formed by a plating method, thereby forming a laminated antenna. It is preferable to form the antenna by a droplet discharge method or a printing method since a conductive film need not be patterned, thereby reducing the number of manufacturing steps.

In addition, the antenna is preferably provided with a connection terminal 135. The antenna can be easily connected with a thin film integrated circuit due to the connection terminal. The connection terminal can be formed by increasing droplets discharged from the nozzle or keeping the nozzle in one position. Note that the connection terminal need not necessarily be provided and the shape and placement thereof is not limited to this embodiment.

The antenna can be formed with a conductive material such as Ag (silver), Al (aluminum), Au (gold), Cu (copper), or Pt (platinum). In the case of using Al or Au, which has relatively high resistance, the wiring resistance may be a concern. However, the wiring resistance can be reduced by thickening the antenna or widening the antenna in the case that a large area is occupied by the antenna. The antenna may be covered with a material having low resistance and be a laminated antenna. In the case of using a conductive material such as Cu, which may diffuse, an insulating film may be formed to cover the formation surface of the antenna and/or the periphery of Cu.

In this embodiment, Ag mixed into tetradecane as a solvent is dropped from the nozzle 160 to form the antenna. At this time, a base film made of titanium oxide (TiOx) may be formed over the antenna substrate to improve adhesion of Ag.

More preferably, pressure is applied to the antenna after the formation to improve the planarity. Accordingly, the antenna can be thinned. A heating means as well as a pressurizing means may be provided, and in that case, pressure treatment and heat treatment can be performed at one time. The heat treatment may be combined with heat treatment for removing the solvent when needed in the case of using a droplet discharge method.

In addition, a groove may be formed on the antenna substrate, and the antenna may be formed in the groove. Since the antenna can be formed in the groove, the antenna substrate and the antenna can be thinned.

Further, the antenna can be formed on both sides of the antenna substrate. In that case, the antenna may be formed on the other side of the antenna substrate by a method similar to that described above. Accordingly, antenna length can be extended, which can increase the communication distance.

A part of the antenna may be formed on the other side of the antenna substrate, depending on the placement of the connection terminal. For example, when the antenna is coiled as shown in FIGS. 1A and 1B, it becomes necessary for a part of the antenna to intersect with another part of the antenna depending on the placement of the connection terminal. At this time, an insulator needs to be interposed so as not to short the antennas. However, the antenna substrate can be used as the insulator.

Subsequently, an opening 113 is formed in the antenna substrate as shown in FIG. 7B. The opening can be formed physically or chemically. In the case of physically forming the opening, a laser can be used. In addition, heat may be applied in order to easily form the opening, and the opening can be formed with a hot needle or the like. In the case of chemically forming the opening, an etching method such as dry etching or wet etching can be used.

The shape of the opening is not limited to a circle and may be a rectangle, a slit, or the like.

The case of attaching the antenna to the IDF chip is described in this embodiment; however, the antenna may be directly formed over the IDF chip. For example, the antenna can be formed in the same layer as the wiring 130.

The contactless IDF chip is described in this embodiment; however, it may be either a contact IDF chip or a hybrid IDF chip.

The IDF chip and the antenna substrate are described as thick in this embodiment to make the embodiment easy to understand. However, they are actually formed very thinly.

Embodiment 2

A specific method of the mode described in Embodiment Mode 2 is described in this embodiment.

FIG. 9A is a top view of 12 IDF chips over an insulating substrate 100, FIG. 9B is a cross-sectional view of line e-f from FIG. 9A, and FIG. 9C is a cross-sectional view of line g-h from FIG. 9A, which crosses a connection region 106. Note that a SAS is used for a separation layer in this embodiment as in Embodiment 1.

As shown in FIG. 9B, thin film transistors 128 n and 128 p, each having an insulating film, a semiconductor film 124 patterned into a desired shape, a gate insulating film 125, and a gate electrode 126, are formed over the insulating substrate 100 with a separation layer 102 therebetween. In addition, a wiring 130 is provided to connect to an impurity region included in the semiconductor film.

The insulating film may have a laminated structure. Here, the insulating film has a first insulating film 121, a second insulating film 122, and a third insulating film 123 as in Embodiment 1.

As in Embodiment 1, the semiconductor film can be formed to contain hydrogen of 1×10¹⁹/cm³ to 1×10²²/cm³, preferably, 1×10¹⁹/cm³ to 5×10²⁰/cm³, unlike a chip formed with a silicon wafer. The hydrogen can provide a so-called dangling-bond termination effect, which reduces dangling bonds in the semiconductor film. Further, the hydrogen can increase flexibility of the IDF chip.

Further, damage or separation due to bending stress of the thin film transistor can be prevented by making a ratio of an area of the patterned semiconductor film in the IDF chip 1% to 30%.

In addition, a first interlayer insulating film 127 and a second interlayer insulating film 129 may be provided as in Embodiment 1. More preferably, a fourth insulating film 131 may be provided to cover the wiring 130.

Thereafter, a groove 105 is selectively formed to leave a connection region 106 in this embodiment. The groove can be formed by dicing, scribing, etching with the use of a mask, or the like as in Embodiment 1. In the case of selectively forming the groove 105 to leave the connection region 106 as shown in FIG. 9C, the groove can be formed by dry etching, wet etching, or the like, after forming a mask pattern by a light exposure step and a development step. In dry etching, an atmospheric plasma method may be used.

In the case of forming the groove by dry etching, wet etching, or the like, conditions such as etching time of the groove can be adjusted in accordance with the placement or the shape of the connection region. Short-time etching reduces influences on other films.

Thus, the groove formed between the IDF chips need not necessarily be formed at every boundary between the IDF chips, but may be formed at intervals of boundaries between the IDF chips.

Subsequently, the separation layer is removed by introducing an etchant as shown in FIGS. 10A to 10C. FIG. 10A is a top view showing a state/process of removing the separation layer by introducing a gas or liquid containing halide typified by ClF₃, FIG. 10B is a cross-sectional view of line e-f from FIG. 10A, and FIG. 10C is a cross-sectional view of line g-h from FIG. 1A, which crosses the connection region 106.

As shown in FIG. 10B, a gas or liquid containing halide typified by ClF₃ is introduced into the groove 105. In this embodiment, ClF₃ (chlorine trifluoride) is used as halide as in Embodiment 1.

When a processing temperature is in the range of 100° C. to 300° C., a reaction rate can be increased. Consequently, the consumption of a ClF₃ gas can be reduced and processing time can be shortened.

The separation layer of a SAS gradually recedes by introducing the etchant. Then, the insulating substrate can be removed as indicated by the arrow.

An etchant, a gas flow rate, temperature, and the like are set so that each layer of the TFT is not etched. ClF₃ used in this embodiment selectively removes the separation layer of a SAS, while each layer of the TFT is not etched by ClF₃ due to the base film and a protective film which are provided above and below the TFT layer and edge portions of the interlayer insulating film, the gate insulating film, the wiring, and the like which are exposed on the side face.

Even when the insulating substrate is removed, the IDF chips are integrated by the connection region. Therefore, the IDF chips are not separated from each other.

Thereafter, the IDF chips are cut by a dicing, scribing, or laser cutting method. Then, the IDF chip may be mounted on an article.

Although the IDF chip can be completed according to the above-described step, a flexible substrate may be attached thereto, as shown in FIGS. 11A to 11C. FIG. 11A is a top view showing a state/process of attaching a flexible substrate 150 with an adhesive 151, FIG. 11B is a cross-sectional view of line e-f from FIG. 1A, and FIG. 11C is a cross-sectional view of line g-h from FIG. 11A, which crosses the connection region 106.

A substrate made of a synthetic resin such as plastic as described above or acrylic can be used as the flexible substrate. In this embodiment, a substrate made of plastic is used.

A thermosetting resin, an ultraviolet curing resin, an epoxy resin, a resin additive, two-sided tape, or the like can be used as the adhesive.

The breaking strength of the IDF chip can be increased by transferring the IDF chip to the flexible substrate.

Subsequently, an antenna substrate is attached thereto as shown in FIGS. 12A to 12C. FIG. 12A is a top view with an antenna substrate 111 attached, FIG. 12B is a cross-sectional view of line e-f from FIG. 12A, and FIG. 12C is a cross-sectional view of line g-h from FIG. 12A, which crosses the connection region 106.

The antenna substrate 111 is provided with an antenna 112 in a position corresponding to the IDF chip as in Embodiment 1. Embodiment 1 may be referred for a detailed manufacturing step of an antenna. In this embodiment, the insulating substrate is separated; therefore, an opening may not be formed on the antenna substrate.

At this time, the IDF chip 104 and the antenna 112 are attached to each other with an anisotropic conductor 141. Instead of using the anisotropic conductor, the IDF chip and the antenna may be attached with the use of an ultrasonic adhesive, an ultraviolet curing resin, two-sided tape, or the like.

Thereafter, the IDF chips are cut by a dicing, scribing, or laser cutting method as shown in FIGS. 13A to 13C, thereby completing the IDF chip formed over the flexible substrate. FIG. 13A is a top view showing a state of the cut IDF chip, FIG. 13B is a cross-sectional view of line e-f from FIG. 13A, and FIG. 13C is a cross-sectional view of line g-h from FIG. 13A, which crosses the connection region 106.

The thus formed IDF chip may be mounted on an article. A thermosetting resin, an ultraviolet curing resin, an epoxy resin, a resin additive, two-sided tape, or the like can be used as an adhesive for mounting.

Although not shown, the IDF chip may be covered with a resin or an insulating film containing nitrogen for protection. In particular, the side face of the IDF chip is preferably covered therewith. The resin or the insulating film containing nitrogen can be made of the same material as an article to be mounted with the IDF chip.

In this embodiment, the IDF chip is mounted with the use of an anisotropic conductor in a “face-down” manner, where the connection terminal of the IDF chip faces the antenna, as described; however, the IDF chip may also be mounted in a “face-up” manner, where the connection terminal faces in the opposite direction to the antenna, as in Embodiment 1.

As described hereinabove, a thin film transistor is formed over the insulating substrate 100, and the insulating substrate 100 is then separated. Preferably, the thin film transistor is further transferred to a flexible substrate. However, the timing of or the number of separations performed is not limited to this embodiment. In addition, the thin film transistor may be mounted on an article (mount article) without transferring the thin film transistor to the flexible substrate. The mounting of the IDF chip in a “face-up” or “face-down” manner is determined in accordance with the number of transfers.

The case of attaching the antenna to the IDF chip is described in this embodiment; however, the antenna may be directly formed over the IDF chip. For example, the antenna can be formed in the same layer as the wiring 130.

The contactless IDF chip is described in this embodiment; however, it may be either a contact IDF chip or a hybrid IDF chip.

The IDF chip and the antenna substrate are described as thick in this embodiment to make the embodiment easy to understand. However, they are actually formed very thinly.

Embodiment 3

The case of using a thin film transistor having a different shape from the above embodiment is described in this embodiment.

FIG. 25A shows the embodiment as described above up to gate electrode formation. Note that the gate electrode has a laminated structure of TaN (tantalum nitride) 126 a and W (tungsten) 126 b in this embodiment. Silicon can also be used for another gate electrode. Subsequently, an interlayer insulating film 127 is formed to cover the gate electrode. In this embodiment, a SiO₂ film is formed to have a thickness of 100 nm by a plasma CVD method.

Subsequently, the entire surface is covered with a resist 44. The resist 44, the interlayer insulating film 127, and the gate insulating film 125 are etched and removed by using an etchback method. Accordingly, a side wall 76 can be formed in a self-aligned manner as shown in FIG. 25B. A mixed gas of CHF₃ and He is used as an etching gas.

When an insulating film is formed on the back of the substrate while forming the interlayer insulating film 127, the insulating film on the back is preferably etched and removed (back treatment) using the resist 44 as a mask.

Note that a method for forming the side wall 76 is not limited to the above. For example, methods shown in FIGS. 26A and 26B can be used. FIG. 26A shows an example in which the insulating film 127 has a laminated structure of two or more layers. The insulating film 127 has a two-layer structure of a SiON (silicon oxynitride) film of 100 nm in thickness and an LTO (Low Temperature Oxide) film of 200 nm in thickness. In this embodiment, the SiON film is formed by a plasma CVD method and a SiO₂ film as the LTO film is formed by a low pressure CVD method. Thereafter, L-shaped and arc-shaped side walls 76 can be formed by performing etchback using the resist 44 as a mask.

FIG. 26B shows an example in which etching is performed to leave the gate insulating film 125 unremoved at the time of etchback. The insulating film 127 in this case may have either a single layer structure or a laminated structure.

The side wall functions as a mask when forming a low concentration impurity region or an undoped off-set region in the lower part of the side wall 76 by doping high concentration of n-type impurities. In either method of forming the side wall described above, etchback conditions can be set in accordance with the width of a low concentration impurity region or an off-set region to be formed.

Subsequently, as shown in FIG. 25C, a resist 77 is newly formed to cover a p-type TFT region, and an impurity element 78 which imparts n-type conductivity (typically, P or As) is added in high concentration using the gate electrode 126 and the side wall 76 as a mask. The doping step is performed with dosages of 1×10¹³/cm² to 5×10¹⁵/cm² and acceleration voltages of 60 keV to 100 keV. According to the doping step, doping (a through doping method) is performed, thereby forming a pair of n-type high concentration impurity regions 79. At this time, an off-set region 65 is formed below the side wall.

Note that the impurity regions may be thermally activated after removing the resist 77 by ashing or the like. For example, a SiON film may be formed to have a thickness of 50 nm and then heat-treated in a nitrogen atmosphere at a temperature of 550° C. for four hours. Further, when a SiNx film containing hydrogen is formed to have a thickness of 100 nm and heat-treated in a nitrogen atmosphere at a temperature of 410° C. for one hour, defects of the crystalline semiconductor film can be improved. This step is referred to as a hydrogenation step by which dangling bonds in, for example, the crystalline semiconductor film can be terminated. In addition, a SiON film may be formed to have a thickness of 600 nm as a cap insulating film for protecting the TFTs. Note that the hydrogenation step may be performed after the formation of the SiON film. In that case, the SiNx film and the SiON film can be sequentially formed. Thus, a three-layer insulating film of SiON, SiNx, and SiON is formed over the TFTs; however, a structure and a material thereof are not limited thereto. These insulating films are preferably formed since they also have the function of protecting the TFTs.

Subsequently, an interlayer insulating film 129 is formed over the TFTs as shown in FIG. 25D. The above embodiment can be referred for a material or a manufacturing method of the interlayer insulating film.

The interlayer insulating film 129 may have a laminated structure. In other words, an insulating film 54 may be laminated over the interlayer insulating film. The insulating film 54 can be formed of a film containing carbon such as DLC (Diamond Like Carbon) or carbon nitride (CN), a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or the like. A plasma CVD method, a sputtering method, or the like can be used as a formation method thereof.

A filler may be mixed into the interlayer insulating film in order to prevent the TFT layer from film separation or cracking due to stress caused by the difference in thermal expansion coefficient between the interlayer insulating film and a conductive material or the like of a wiring to be formed later. The filler can control thermal expansion.

Then, after forming a resist, a contact hole is formed by etching. After that, a wiring 130 for connecting the TFTs and a connecting wiring 21 for connecting the TFT to an external antenna are formed. Although a mixed gas of CHF₃ and He is used as an etching gas to form the contact hole, the invention is not limited thereto. The wiring 130 and the connecting wiring 21 may be simultaneously formed by using the same material, or may be separately formed. In this embodiment, the wiring 130 connected to the TFTs is to have a five-layer structure of Ti, TiN, Al—Si, Ti, and TiN, and is formed by a sputtering method and then patterned.

When Si is mixed into the Al layer, the occurrence of hillocks can be prevented while resist baking during wiring patterning. Instead of Si, Cu of approximately 0.5% may be mixed as well. The occurrence of hillocks can be further suppressed by sandwiching the Al—Si layer between Ti and TiN. Note that it is desirable to use a mask formed of an inorganic material such as SiON in patterning. A material and a forming method of the wiring are not limited thereto. The above-described material which is used for the gate electrode may be employed. At this time, a protective film 80 may be provided over the wiring, and an opening may be formed in the connection region.

Through the above-described steps, the IDF chip with TFTs is completed. A top gate structure is described in this embodiment; however, a bottom gate (inversely staggered) structure may be adopted as well.

As shown in FIG. 25D, it is desirable to adjust the thickness of the base film and the interlayer insulating film in the IDF chip so that a distance (t_(under)) from the semiconductor layer to the bottom of the base film may be equal to or approximately equal to a distance (t_(over)) from the semiconductor layer to the top of the interlayer insulating film. Stress on the semiconductor layer can be relieved and occurrence of cracks can be prevented by placing the semiconductor layer at the center of the IDF chip in this manner.

Thereafter, a groove can be formed to separate the insulating substrate, and an antenna can be formed as in the above embodiment.

The thin film transistor having a side wall, which is described in this embodiment, can be freely combined with the above embodiment modes and the above embodiments.

Embodiment 4

A method for manufacturing a thin film integrated circuit, which is different from the modes described in Embodiments 1 and 2, is described in this embodiment.

As shown in FIG. 14A, IDF chips integrated by a connection region 106 is prepared according to Embodiment Mode 2 or Embodiment 2. The IDF chips are provided with bumps 201 which are formed of the same material as a wiring 130.

In addition, a second substrate 202 provided with wirings 203 is prepared. As the second substrate, a substrate made of glass such as barium borosilicate glass or alumino borosilicate glass; a quartz substrate; or the like can be used. A substrate made of a synthetic resin such as plastic typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyeter sulfone (PES) or acrylic can be used as another substrate having an insulating surface.

As shown in FIG. 14B, with the use of an adhesive 204, the integrated IDF chips are attached to the second substrate 202 provided with the wirings 203. At this time, the IDF chips are attached to the second substrate so that the bumps 201 are connected to the wirings 203. An anisotropic conductor can be used as the adhesive 204. Instead of an anisotropic conductor, the IDF chips may be attached with the use of an ultrasonic adhesive, an ultraviolet curing resin, two-sided tape, or the like.

As shown in FIG. 14C, the IDF chips are cut by a dicing, scribing, or laser cutting method.

Thereafter, an antenna terminal 205 is formed as shown in FIG. 14D. The antenna terminal can be formed by a droplet discharge method, a sputtering method, a CVD method, or the like.

Then, an antenna substrate 111, provided with an antenna 112, is attached to the IDF chip, as shown in FIG. 14E. The above embodiment mode and embodiment can be referred for a material or a manufacturing method of the antenna or the antenna substrate. The antenna substrate may be made of the same material as an article to be mounted with the IDF chip.

As described above, the IDF chip can take various mounting forms of antennas. In other words, the IDF chip goes through manufacturing process in an integrated state, and has no particular limitation on the mounting form or the mounting method of an antenna.

The contactless IDF chip is described in this embodiment; however, it may be either a contact IDF chip or a hybrid IDF chip as described in Embodiment 1 or 2.

The IDF chip and the antenna substrate are described as thick in this embodiment to make the embodiment easy to understand. However, they are actually formed very thinly.

Embodiment 5

Various forms of IDF chips are described in this embodiment.

As shown in FIG. 22A, an IDF chip 104 and an antenna 112 which is formed over an antenna substrate 111 are connected to each other with a connection terminal, for example, a bump 109 therebetween, by using an anisotorpic conductor 141 with a conductor 140. Instead of an anisotropic conductor, an ultrasonic adhesive, an ultraviolet curing resin, two-sided tape, or the like may be used.

As shown in FIG. 22B, an IDF chip is attached to a flexible substrate 150 by an adhesive 151. A thermosetting resin, an ultraviolet curing resin, an epoxy resin, a resin additive, two-sided tape, or the like can be used as the adhesive.

A plurality of antenna substrates may be provided. For example, antenna substrates provided with antennas 112 are provided on both sides of the IDF chip as shown in FIG. 22C. Accordingly, antenna length can be extended, which can increase a communication distance. At this time, a conductive film 250 is formed to connect the antenna on one side to the antenna on the other side. For example, droplets having conductors are selectively discharged between the antenna substrates by a droplet discharge method. Thereafter, an insulating film 251 is preferably formed to protect the conductive film 250.

In addition, a structure for connecting the antenna on one side to the antenna on the other side is not limited to this embodiment. For example, the antenna on one side and the antenna on the other side may each be connected to the IDF chip through the bump 109.

As described above, the IDF chip mounted with the antenna can be completed.

Note that the IDF chip of the invention is not limited to the forms described in this embodiment. For example, there are modes of forming the antenna in the same layer as the conductive film included in the thin film transistor and forming the antenna, without using the antenna substrate, over the IDF chip.

Embodiment 6

Forms of articles mounted with IDF chips are described in this embodiment. Note that the mounting position of the IDF chip, the shape of an article to be mounted with the IDF chip, and the number of IDF chips to be mounted are not limited to this embodiment.

FIGS. 15A and 15B show the case of attaching the IDF chip to a label of food or drink and mounting the IDF chip on a container of the food or drink, for example, a beer bottle 181.

As shown in FIG. 15A, an IDF chip 104 provided with an antenna 112 is attached to a label 180 by two-sided tape or the like. When the label has adhesiveness, the IDF chip may be directly attached to the adhesive label.

Such goods pass by a reader/writer 182 on a conveyor belt 183 or the like as shown in FIG. 15B; accordingly, information can be inputted or read. Existing information can be rewritten depending on the kind of a memory formed in the IDF chip.

Since information can be inputted to or read out of the IDF chip provided with the antenna without contact, information can be managed by a reader/writer with goods packed in a cardboard box or the like.

Such goods mounted with the IDF chips can largely reduce personnel cost in distribution. Furthermore, human error can also be reduced.

Information in the IDF chip mounted on goods as described above ranges from basic information relating to production or manufacture such as place, processor/manufacturer, date, and the like, to allergy information, main component, advertisement, and the like. In addition, an information storage means such as a bar code or a magnetic tape may be used to increase the amount of information or to improve security. In the case of using the IDF chip in combination with, for example, a bar code, they are preferably appropriately used in accordance with the purpose. For example, information unnecessary to rewrite, such as the basic information, may be inputted to a bar code, and rewritable information may be inputted to an IDF chip.

When a ROM or the like, to which data cannot be rewritten, is formed in a memory included in an ID chip, it is possible to prevent forgery of securities: banknotes and checks, and certificates: a family register, a resident card, a name/business card, a traveler's check, and a passport.

The case of mounting an IDF chip 602 on a bag 601 is described as an example of anti-theft measures. For example, the IDF chip can be mounted on the bottom or the side of the bag as shown in FIG. 27. Since the IDF chip is extremely thin and small, it can be mounted while maintaining the attractive design of the bag. In addition, the IDF chip is light transmitting; thus, it cannot be easily recognized by a thief. Accordingly, there is no fear that the ID chip will be removed by a thief.

In the case where such a bag mounted with an IDF chip is stolen, information on the actual location of the bag can be obtained by using, for example, a GPS (Global Positioning System). Note that the GPS is a system for determining the position based on the time difference found by receiving a signal transmitted from a GPS satellite.

In addition to the stolen article, information on the actual location of lost property or thing left behind, can be obtained by using the GPS.

In addition, the IDF chip can be mounted on a vehicle such as an automobile or a bicycle, a watch, accessories, and the like as well as the bag.

FIG. 16A shows a banknote 301 mounted with an IDF chip. In FIG. 16A, an IDF chip 302 is fixed inside the banknote, but it may be formed on the surface. This is because the IDF chip is light transmitting and does not disturb printing or the like even when formed over the surface.

In addition, the IDF chip may be mounted on securities other than a banknote. For example, it may be mounted on a coin. Mounting the IDF chip on a banknote or a coin can be helpful in preventing forgery as well as improve accuracy of identification of the banknote or the coin in a vending machine or the like.

FIG. 16B shows a check 311 mounted with an IDF chip. In FIG. 16B, an IDF chip 312 is provided on the surface of the check. Since the IDF chip is light transmitting, it may be provided on the surface of the check. Naturally, the IDF chip may also be fixed inside the check.

FIG. 16C shows a stock certificate 321 mounted with an IDF chip. Although an IDF chip 322 is fixed inside the stock certificate in FIG. 16C, it may also be provided on the surface thereof. The size, the shape, and the mounting position of the IDF chip are not exclusively limited. However, the ID chip may be made larger in the case of including a large amount of information. Even in such a case, the IDF chip is light transmitting; therefore, it does not disturb printing wherever it is mounted.

A banknote, a check, a stock certificate, or the like may be printed by using ink including the IDF chip. Further, a plurality of IDF chips may be scattered when mixing a material of a banknote, a check, a stock certificate, or the like with chemicals to form a banknote, a check, a stock certificate, or the like mounted with the plurality of IDF chips. Since the IDF chip can be manufactured at a low cost, a plurality of IDF chips can be mounted on the banknote, the check, the stock certificate, or the like without adversely affecting the manufacturing cost thereof.

As described above, the IDF chip is formed of a thin film integrated circuit that is drastically reduced in thickness; thus, the IDF chip can be mounted on a very thin paper-like article. Therefore, the attractive design of an article can be maintained. In addition, since the IDF chip is light transmitting, it may be mounted on the surface of an article.

FIG. 17A shows a book 331 mounted with an IDF chip. An IDF chip 332 can be provided on the surface of or inside a cover of the book. Alternatively, the IDF chip may be mounted on any page of the book.

FIG. 17B shows a DVD 341 mounted with an IDF chip. An IDF chip 342 can be provided on the surface of or inside the packaging of the DVD. Naturally, the IDF chip may be mounted on a product such as a CD or a videotape as well as a DVD.

When the IDF chip is mounted on such an article of which rental service is actively performed, the lending and return processes can be performed more simply and in a shorter time. In addition, product information such as contents, advertisement, cast, and the like can be written in the IDF chip as data.

The IDF chip can be changed in size and shape, to some extent, in accordance with the size and shape of an object to which the IDF chip is attached. Accordingly, applications of the IDF chips are not limited to those described in this embodiment, and other various applications are possible.

By mounting the IDF chip on a personal belonging, the belonging can be located even when it is lost or stolen.

The IDF chip may be fixed to a piece of wrapping paper for wrapping a belonging. Further, a message can be written in the IDF chip as audio data. In that case, the data is read by a reader and the message can be gotten by a reproducing device. In addition, various information can be provided through a network by reading data with a reader.

The case of mounting an IDF chip on goods such as food for safety management is described.

FIG. 28 shows a package 611 of meat attached with a label 613 mounted with an IDF chip 612. The IDF chip may be mounted on the surface of or inside the label. In the case of fresh food such as vegetables, the IDF chip may also be mounted on a piece of cellophane for covering fresh food.

The IDF chip can store basic information relating to the product such as a production area, a producer, a processing date, and an expiration date. Further, an application such as a serving suggestion with the product may be stored. Since such basic information need not be rewritten, it may be stored in an unrewritable memory such as an MROM. Such an application may also be stored in a rewritable and erasable memory such as an EEROM.

In addition, it is important to be able to know the condition of animals and plants before processing in order to manage food safety. Therefore, the IDF chip may be implanted in animals and plants and the information relating to the animals and plants in the IDF chip may be obtained by a reader. Information on animals and plants may include a breeding place, feed, a breeder, and a record of infection with communicable diseases.

When the price of a product is stored in the IDF chip, the product can be paid for more simply and in a shorter time than the case of using a conventional bar code. In other words, a plurality of products mounted with the IDF chips can be paid for at one time. However, the reader needs to have an anti-collision function to manage the case of reading such a plurality of IDF chips at one time.

Further, the products can be paid for at the cash register even when there is a distance between the products and the cash register depending on the communication distance of the IDF chip. In addition, the IDF chip is also helpful in preventing shoplifting and the like.

Moreover, the IDF chip can be used in combination with other information media such as a bar code and a magnetic tape. For example, basic information which is unnecessary to rewrite may be stored in the IDF chip, and information to be renewed, for example, information on discount price and special price may be stored in a bar code. This is because information in the bar code can be easily changed, unlike the IDF chip.

Mounting the IDF chip in this manner can increase the amount of information given to consumers; thus, consumers can purchase products with ease.

Described next are a product mounted with an IDF chip and a manufacturing apparatus (manufacturing robot) which is controlled based on the information in the IDF chip, in order to perform manufacturing control.

These days, customized products are often manufactured, and they are manufactured on a production line based on the customized information of the products to be produced. For example, in a production line of cars that provides free color choice of doors, an IDF chip is mounted on a part of each car and controls a painting apparatus based on the information in the IDF chip. Thus, a customized car can be manufactured. When the IDF chip is mounted, there is no need to adjust the order of and the number of cars to be put into a production line and to be painted in the same color in advance. Furthermore, it is not necessary to set a program for controlling a painting apparatus in accordance with the order and number of cars. In other words, a manufacturing apparatus can operate individually based on information in the IDF chip mounted on each car.

As described above, the IDF chip can be applied to various fields. Based on information stored in the IDF chip, specific information for manufacturing can be obtained and a manufacturing apparatus can be controlled based on the information.

Described hereinafter is a mode of using a card 621 mounted with an IDF chip 622 as electronic money. FIG. 29 shows that the card 621 is used to make a payment. FIG. 29 also shows a cash register 623 and a reader/writer 624. The IDF chip 622 stores information on the amount deposited into the card 621. The information on the amount can be read without contact by the reader/writer 624 and transferred to the cash register 623. The cash register 623 verifies that the amount deposited into the card 621 is more than the amount to be paid for, and thus payment is made. Then, the information of the remaining amount of the money after the payment is transmitted to the reader/writer 624 and is written in the IDF chip 622 of the card 621 by the reader/writer 624.

Note that the reader/writer 624 may be equipped with a key pad 625 for inputting a personal identification number and the like, thereby preventing the card 621 from being used to make payment by a third party without notice.

The IDF chip is preferably placed at the center of an article to be mounted therewith (mount article) and is preferably surrounded by a material of the article. Accordingly, the mechanical strength of the IDF chip can be improved. Specifically, when the thickness of the mount article is denoted by D, an interposed position of the IDF chip (center of the IDF chip) X may be set to satisfy (½)·D−30 μm<X<(½)·D+30 μm.

Even when an antenna is separately formed, the IDF chip is preferably placed in the above position.

As described above, it is desirable to adjust the thickness of the base film and the interlayer insulating film in the IDF chip so that a distance (t_(under)) from the semiconductor layer to the bottom of the base film may be equal to or approximately equal to a distance (t_(over)) from the semiconductor layer to the top of the interlayer insulating film. Thus, stress on the semiconductor layer can be relieved and the occurrence of cracks can be prevented when the IDF chip is placed at the center of the article and the semiconductor layer is placed at the center of the IDF chip.

In addition, the IDF chip and the antenna may be separately mounted on the article. There is no limitation on a mounting area and the degree of freedom for design is increased when the IDF chip and the antenna are mounted on different faces. The antenna in this case can be directly mounted on the article. Thereafter, the connection terminal of the antenna is joined to a connection terminal of the IDF chip. At this time, they can be joined to each other with an anisotropic conductor.

Embodiment 7

An IDF chip is assumed to have a measure of area in some cases and is highly flexible as compared with a chip formed from a silicon wafer; therefore, the damage in a bent state needs to be considered. Correspondingly, in this embodiment, the state where a banknote equipped with an IDF chip is bent will be described.

FIG. 19A shows a banknote 301 which is a IDF chip mount article and is bent in the arrow direction 280. Generally, a thin film material easily bends or can be easily bent in the longitudinal direction; accordingly, the case of bending in the longitudinal direction will be described in this embodiment.

An IDF chip 104 in such a state is shown in FIG. 19B. The IDF chip has a plurality of thin film transistors 230 and the thin film transistors are arranged so that a carrier flow direction 281 and the arrow direction (bending direction) 280 are perpendicular. In other words, a source region 230(s), a channel forming region 230(c), and a drain region 230(d) of each thin film transistor are arranged so as to be perpendicular to the bending direction 280. As a result, damage or separation due to bending stress of the thin film transistor can be prevented.

In the case of using a crystalline semiconductor film using laser irradiation as a semiconductor film, a laser scanning direction 283 is also set so as to be perpendicular to the bending direction 280. For example, as shown in FIG. 23B, in the case of moving a laser irradiation region (spot) 282 to crystallize the entire surface, the laser scanning direction 283 (major axis side) is set perpendicular to the bending direction 280.

By bending the IDF chip in such a direction, the IDF chip, particularly, a thin film transistor is not damaged. Further, the grain boundaries in the direction of the carrier flow can be reduced to a minimum. Consequently, the electrical characteristics of the thin film transistors, particularly, the mobility can be improved.

Further, damage or separation due to bending stress of the thin film transistor can be prevented by making a ratio of an area of the patterned semiconductor film in the IDF chip 1% to 30%.

The contactless IDF chip is described in this embodiment; however, it may be either a contact IDF chip or a hybrid IDF chip.

Embodiment 8

Application mode using an article equipped with a thin film integrated circuit is described.

FIG. 18A shows information flow through a medicine bottle 401 equipped with an IDF chip 402 attached to a label 403, a reader/writer 410, a personal computer 420 having a display portion 421, and the like. Information in the IDF chip, for example, a dose, an effect, a side effect, allergy, and the like is inputted into the personal computer through the reader/writer, and the information can be confirmed on the display portion 421.

The IDF chip may include information such as business advertisement, for example, a home page address. In that case, an Internet browser is activated and the address is inputted through the reader/writer; then, the homepage can be seen. By reading information recorded in an IDF chip, an input error can be avoided as compared with the case where the information is inputted manually.

The information on medicine can be read with the use of a portable electronic device having a function of a reader/writer, typified by a cellular phone or a PDA. For example, a coil serving as an antenna 431 of a cellular phone 430 is designed to serve also as an antenna of a reader/writer. The information recorded in the IDF chip can be confirmed on a display portion 432 of the cellular phone.

FIG. 18B shows a circuit configuration of an IDF chip and a reader/writer.

First, an IDF chip 104 includes an antenna coil 501, a capacitor 502, a demodulation circuit 503, a modulation circuit 504, a rectifier circuit 505, a microprocessor 506, a memory 507, and a switch 508 for applying a load to the antenna coil 501. These circuits and the microprocessor can be formed with a thin film integrated circuit. The number of the memory 507 is not limited to one but a plurality of memories may be used.

A reader/writer 410 includes an antenna coil 511, a modulation circuit 512, and an oscillating means 513, which contribute to the generation of a transmit signal. The reader/writer 410 further includes a detection demodulation circuit 514 which detects, amplifies, and modulates a received signal. Since a signal received from the IDF chip is extremely weak, the received signal is preferably separated and amplified with the use of a filter or the like. Subsequently, the received signal is transmitted to a gate ASIC (application-specific integrated circuit) 515.

The data inputted to the gate ASIC is transmitted to a microprocessor 516 and processed. As necessary, mutual transmission of a signal is performed between the microprocessor 516 and a memory 517, thereby achieving predetermined processing. A program, data, and the like which are used in the microprocessor 516 are stored in the memory 517. Moreover, the memory can be used as an operation area in processing. Thereafter, signal transmission between the microprocessor and a signal interface 519 can be performed. Further, a power source 518 for such mutual signal exchange is provided.

The microprocessor 516, the memory 517, and the signal interface 519 can be provided in a personal computer or a telephone itself.

The reader/writer may have an anti-collision function.

Further, an electronic device such as a cellular phone which also serves as a reader/writer may include an antenna coil 511, a modulation circuit 512, an oscillating means 513, a detection demodulation circuit 514, a gate ASIC 515, a microprocessor 516, a memory 517, a power source 518, and a signal interface 519.

Naturally, the circuits above and the like can be formed in a personal computer to provide a reader/writer function.

A signal transmitted from the gate ASIC 515 as electric waves through the modulation circuit 512 is converted into an AC electrical signal by electromagnetic induction in the antenna coil 501. The AC electrical signal is demodulated in the demodulation circuit 503 and transmitted to the microprocessor 506. Further, power supply voltage is generated with the use of the AC electrical signal in the rectifier circuit 505, and supplied to the microprocessor 506.

In the microprocessor 506, a variety of processing is performed in accordance with inputted signals. The memory 507 can be used not only for storing a program, data and the like used in the microprocessor 506 but also as an operation area in processing. A signal transmitted from the microprocessor 506 to the modulation circuit 504 is modulated into an AC electrical signal. The switch 508 can apply a load to the antenna coil 501 in accordance with the AC electrical signal from the modulation circuit 504. The reader/writer receives the load applied to the antenna coil 501 by electric waves, thereby consequently reading a signal from the microprocessor 506.

The circuit configurations of the IDF chip and the reader/writer shown in FIG. 18B is only an example, and the present invention is not limited thereto. A method for transmitting a signal is not limited to the electromagnetic induction method shown in this embodiment. An electromagnetic coupling method, a microwave method, or other transmitting methods may also be adopted. Further, an IDF chip of the present invention may have a function such as a GPS.

This application is based on Japanese Patent Application serial No. 2004-031064 filed in Japan Patent Office on Feb. 6, 2004, the contents of which are hereby incorporated by reference. 

1. A method for manufacturing a thin film integrated circuit, comprising the steps of: forming a separation layer over an insulating substrate; forming at least two thin film integrated circuits over the separation layer; forming a groove between the two thin film integrated circuits to expose the separation layer; attaching an antenna substrate provided with an opening and an antenna over the two thin film integrated circuits; and separating the insulating substrate by introducing an etchant into the opening and removing the separation layer, wherein the two thin film integrated circuits are integrated by the antenna substrate.
 2. A method for manufacturing a thin film integrated circuit, comprising the steps of: forming a separation layer over an insulating substrate; forming at least two thin film integrated circuits over the separation layer; selectively forming a groove between the two thin film integrated circuits to expose a part of the separation layer and form a connection region which is a part of the two thin film integrated circuits; and separating the insulating substrate by introducing an etchant into the opening and removing the separation layer, wherein the two thin film integrated circuits are integrated by the connection region.
 3. A method for manufacturing a thin film integrated circuit, comprising the steps of: forming a separation layer over an insulating substrate; forming at least two thin film integrated circuits over the separation layer; selectively forming a groove between the two thin film integrated circuits to expose a part of the separation layer and form a connection region which is a part of the two thin film integrated circuits; attaching an antenna substrate provided with an opening and an antenna over the two thin film integrated circuits; and separating the insulating substrate by introducing an etchant into the groove and the opening and removing the separation layer, wherein the two thin film integrated circuits are integrated by the antenna substrate.
 4. The method for manufacturing a thin film integrated circuit according to claim 1, further comprising the steps of: attaching the two thin film integrated circuits to a flexible substrate.
 5. The method for manufacturing a thin film integrated circuit according to claim 2, further comprising the steps of: attaching an antenna to the two thin film integrated circuits.
 6. The method for manufacturing a thin film integrated circuit according to claim 2, further comprising the steps of: attaching an antenna to the two thin film integrated circuits; and attaching the two thin film integrated circuits to a flexible substrate.
 7. The method for manufacturing a thin film integrated circuit according to claim 3, further comprising the steps of: attaching the two thin film integrated circuits to a flexible substrate.
 8. The method for manufacturing a thin film integrated circuit according to claim 1, wherein each of the two thin film integrated circuits comprises a thin film transistor and an insulating film containing nitrogen provided over and under the thin film transistor.
 9. The method for manufacturing a thin film integrated circuit according to claim 2, wherein each of the thin film integrated circuits comprises a thin film transistor and an insulating film containing nitrogen provided over and under the thin film transistor.
 10. The method for manufacturing a thin film integrated circuit according to claim 3, wherein each of the thin film integrated circuits comprises a thin film transistor and an insulating film containing nitrogen provided over and under the thin film transistor.
 11. The method for manufacturing a thin film integrated circuit according to claim 1, wherein the etchant is a gas or a liquid including halide typified by ClF₃.
 12. The method for manufacturing a thin film integrated circuit according to claim 2, wherein the etchant is a gas or a liquid including halide typified by ClF₃.
 13. The method for manufacturing a thin film integrated circuit according to claim 3, wherein the etchant is a gas or a liquid including halide typified by ClF₃.
 14. The method for manufacturing a thin film integrated circuit according to claim 1, wherein the insulating substrate is a glass substrate, a quartz substrate, or a substrate made of a synthetic resin such as plastic or acrylic.
 15. The method for manufacturing a thin film integrated circuit according to claim 2, wherein the insulating substrate is a glass substrate, a quartz substrate, or a substrate made of a synthetic resin such as plastic or acrylic.
 16. The method for manufacturing a thin film integrated circuit according to claim 3, wherein the insulating substrate is a glass substrate, a quartz substrate, or a substrate made of a synthetic resin such as plastic or acrylic.
 17. The method for manufacturing a thin film integrated circuit according to claim 1, wherein a mounting position of each of the two thin film integrated circuits X satisfies (½)·D−30 μm<X<(½)·D+30 μm when a thickness of a mount article is denoted by D.
 18. The method for manufacturing a thin film integrated circuit according to claim 2, wherein a mounting position of each of the two thin film integrated circuits X satisfies (½)·D−30 μm<X<(½)·D+30 μm when a thickness of a mount article is denoted by D.
 19. The method for manufacturing a thin film integrated circuit according to claim 3, wherein a mounting position of each of the two thin film integrated circuits X satisfies (½)·D−30 μm<X<(½)·D+30 μm when a thickness of a mount article is denoted by D.
 20. The method for manufacturing a thin film integrated circuit according to claim 1, wherein the antenna is attached to the two thin film integrated circuits by an anisotropic conductor, an ultrasonic adhesive, or an ultraviolet curing resin.
 21. The method for manufacturing a thin film integrated circuit according to claim 3, wherein the antenna is attached to the two thin film integrated circuits by an anisotropic conductor, an ultrasonic adhesive, or an ultraviolet curing resin.
 22. The method for manufacturing a thin film integrated circuit according to claim 5, wherein the antenna is attached to the two thin film integrated circuits by an anisotropic conductor, an ultrasonic adhesive, or an ultraviolet curing resin.
 23. The method for manufacturing a thin film integrated circuit according to claim 1, wherein the antenna is formed by a method selected from the group consisting of a droplet discharge method, a sputtering method, a printing method, a plating method, a photolithography method, an evaporation method using a metal mask, and a combination thereof.
 24. The method for manufacturing a thin film integrated circuit according to claim 3, wherein the antenna is formed by a method selected from the group consisting of a droplet discharge method, a sputtering method, a printing method, a plating method, a photolithography method, an evaporation method using a metal mask, and a combination thereof.
 25. The method for manufacturing a thin film integrated circuit according to claim 5, wherein the antenna is formed by a method selected from the group consisting of a droplet discharge method, a sputtering method, a printing method, a plating method, a photolithography method, an evaporation method using a metal mask, and a combination thereof.
 26. The method for manufacturing a thin film integrated circuit according to claim 1, wherein the separation layer is an amorphous semiconductor, a semi-amorphous semiconductor, a microcrystalline semiconductor, or a crystalline semiconductor.
 27. The method for manufacturing a thin film integrated circuit according to claim 2, wherein the separation layer is an amorphous semiconductor, a semi-amorphous semiconductor, a microcrystalline semiconductor, or a crystalline semiconductor.
 28. The method for manufacturing a thin film integrated circuit according to claim 3, wherein the separation layer is an amorphous semiconductor, a semi-amorphous semiconductor, a microcrystalline semiconductor, or a crystalline semiconductor.
 29. The method for manufacturing a thin film integrated circuit according to claim 1, wherein the two thin film integrated circuits have a thickness of 0.3 μm to 3 μm.
 30. The method for manufacturing a thin film integrated circuit according to claim 2, wherein the two thin film integrated circuits have a thickness of 0.3 μm to 3 μm.
 31. The method for manufacturing a thin film integrated circuit according to claim 3, wherein the two thin film integrated circuits have a thickness of 0.3 μm to 3 μm.
 32. The method for manufacturing a thin film integrated circuit according to claim 1, wherein the two thin film integrated circuits are 5 mm squared or less.
 33. The method for manufacturing a thin film integrated circuit according to claim 2, wherein the two thin film integrated circuits are 5 mm squared or less.
 34. The method for manufacturing a thin film integrated circuit according to claim 3, wherein the two thin film integrated circuits are 5 mm squared or less.
 35. The method for manufacturing a thin film integrated circuit according to claim 1, wherein each of the two thin film integrated circuits includes a semiconductor film having a hydrogen concentration of 1×10¹⁹/cm³ to 5×10²⁰/cm³.
 36. The method for manufacturing a thin film integrated circuit according to claim 2, wherein each of the two thin film integrated circuits includes a semiconductor film having a hydrogen concentration of 1×10¹⁹/cm³ to 5×10²⁰/cm³.
 37. The method for manufacturing a thin film integrated circuit according to claim 3, wherein each of the two thin film integrated circuits includes a semiconductor film having a hydrogen concentration of 1×10¹⁹/cm³ to 5×10²⁰/cm³.
 38. The method for manufacturing a thin film integrated circuit according to claim 35, wherein the semiconductor film has a thickness of 0.2 μm or less.
 39. The method for manufacturing a thin film integrated circuit according to claim 36, wherein the semiconductor film has a thickness of 0.2 μm or less.
 40. The method for manufacturing a thin film integrated circuit according to claim 37, wherein the semiconductor film has a thickness of 0.2 μm or less.
 41. The method for manufacturing a thin film integrated circuit according to claim 35, wherein the semiconductor film comprises a source region, a drain region, and a channel formation region and, wherein the source region, the drain region, and the channel formation region are formed to be perpendicular to a bending direction of a mount article.
 42. The method for manufacturing a thin film integrated circuit according to claim 36, wherein the semiconductor film comprises a source region, a drain region, and a channel formation region and, wherein the source region, the drain region, and the channel formation region are formed to be perpendicular to a bending direction of a mount article.
 43. The method for manufacturing a thin film integrated circuit according to claim 37, wherein the semiconductor film comprises a source region, a drain region, and a channel formation region and, wherein the source region, the drain region, and the channel formation region are formed to be perpendicular to a bending direction of a mount article.
 44. The method for manufacturing a thin film integrated circuit according to claim 1, wherein a thin film integrated circuit is formed by cutting the two thin film integrated circuits by a dicing, a scribing, or a: laser cutting method.
 45. The method for manufacturing a thin film integrated circuit according to claim 2, wherein a thin film integrated circuit is formed by cutting the two thin film integrated circuits by a dicing, a scribing, or a laser cutting method.
 46. The method for manufacturing a thin film integrated circuit according to claim 3, wherein a thin film integrated circuit is formed by cutting the two thin film integrated circuits by a dicing, a scribing, or a laser cutting method.
 47. An element substrate comprising: an insulating substrate; a separation layer over the insulating substrate; at least two thin film integrated circuits over the separation layer; and an antenna substrate provided opposite to the insulating substrate, wherein the antenna substrate includes an antenna and an opening, and wherein a groove is provided between the two thin film integrated circuits to correspond to the opening.
 48. An element substrate comprising: an insulating substrate; a separation layer over the insulating substrate; at least two thin film integrated circuits over the separation layer; a connection region; and an antenna substrate provided opposite to the insulating substrate, wherein the antenna substrate includes an antenna and a first opening, wherein a groove is provided between the two thin film integrated circuits to correspond to the first opening, wherein a second opening is provided in the two thin film integrated circuits, and wherein the two thin film integrated circuits are integrated by the connection region.
 49. The element substrate according to claim 47, wherein each of the two thin film integrated circuits comprises a thin film transistor and a layer having an insulating film containing nitrogen provided over and under the two thin film integrated circuits.
 50. The element substrate according to claim 48, wherein each of the two thin film integrated circuits comprises a thin film transistor and a layer having an insulating film containing nitrogen provided over and under the two thin film integrated circuits.
 51. The element substrate according to claim 47, wherein the separation layer is an amorphous semiconductor, a semi-amorphous semiconductor, a microcrystalline semiconductor, or a crystalline semiconductor.
 52. The element substrate according to claim 48, wherein the separation layer is an amorphous semiconductor, a semi-amorphous semiconductor, a microcrystalline semiconductor, or a crystalline semiconductor.
 53. The element substrate according to claim 47, wherein the two thin film integrated circuits have a thickness of 0.3 μm to 3 μm.
 54. The element substrate according to claim 48, wherein the two thin film integrated circuits have a thickness of 0.3 μm to 3 μm.
 55. The element substrate according to claim 47, Wherein each of the two thin film integrated circuits includes a semiconductor film having a hydrogen concentration of 1×10¹⁹/cm³ to 5×10²⁰/cm³.
 56. The element substrate according to claim 48, Wherein each of the two thin film integrated circuits includes a semiconductor film having a hydrogen concentration of 1×10¹⁹/cm³ to 5×10²⁰/cm³.
 57. The element substrate according to claim 55, wherein the semiconductor film has a thickness of 0.2 μm or less.
 58. The element substrate according to claim 56, wherein the semiconductor film has a thickness of 0.2 μm or less.
 59. The element substrate according to claim 47, wherein the element substrate is mounted with a product selected from the group consisting of a label, a banknote, a check, a stock certificate and a card.
 60. The element substrate according to claim 48, wherein the element substrate is mounted with a product selected from the group consisting of a label, a banknote, a check, a stock certificate and a card. 